When serial signals are transmitted differentially, transmission-line loss increases with frequency and phase lag ascribable to the transmission line also increases with frequency. On the receiving side, therefore, the higher the frequency, the more jitter increases and the more the eye aperture ratio declines. Accordingly, Patent Document 1 discloses a signal transmission circuit equipped with an inductor having one end thereof connected to the receiving side of a transmission line and the other end thereof connected to a terminating resistor. In accordance with such a signal transmission circuit, phase lag of the transmission line is compensated for by the inductor, jitter can be reduced and the eye aperture ratio enlarged. Patent Document 1 describes that means such as a chip inductor or metal wiring is employed as the inductor.
A level shifter constituted by a transistor source follower is often used on the receiving side of differential transmission for the purpose of adjusting the common level of the receive differential signals. An example of a circuit in which the load of the source follower is a current source is described in Non-Patent Document 1 as the arrangement of the level shifter relaying upon the source follower.
FIG. 8 is a typical example of the circuit diagram of a level shift circuit described in Non-Patent Document 1. As shown in FIG. 8, a PMOS transistor MP101 has a gate to which an input signal VI is supplied, a drain connected to ground and a source connected to the drain of a PMOS transistor MP102 and from which an output signal VO is produced. The PMOS transistor MP102 has a gate to which a bias voltage Vb is applied and a source connected to a power supply VDD. A capacitance element Cload represents a load capacitance connected to the source of the PMOS transistor MP101.
Related Patent Document 2 describes an active inductance circuit having a small number of elements and capable of low-voltage operation. The active inductance circuit includes a first transistor, a second transistor having a polarity different from that of the first transistor, a capacitor and a current source. A first signal terminal of the first transistor is connected to an output terminal, a control terminal of the second transistor is connected to the first signal terminal of the first transistor, a control terminal of the first transistor is connected to a second signal terminal of the second transistor, and the second signal terminal of the second transistor is connected to a terminal of the current source and to a terminal of the capacitor.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP2006-254303A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP2004-343373A
[Non-Patent Document 1]
Xianping Fan and P. K. Chan, “Analysis and Design of Low-Distortion CMOS Source Followers”, IEEE Transactions on Circuit and System, Vol. 52, No. 8, August 2005, pp. 1489-1501